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Hardware Platforms
Overview |
High Density T1/E1 Boards |
Basic & Optional Features |
Screenshots
Specifications |
Latest Software |
Application Notes |
Buyer's Guide |
VQT
T1/E1 Software Ver 5.13 is Now Available! Download it here
Overview
The ULTRA T1 (E1) is an enhanced third-generation product that consolidates the essential pieces of industry-standard test
equipment into a powerful, PC-Based T1 and E1 solution. Utilizing familiar computer user interfaces, it provides comprehensive
and versatile T1 or E1 testing capability at a competitive price.
The ULTRA T1 (E1) Card transforms your PC into a sophisticated T1 or E1 analyzer. Prior versions of the Ultra T1(E1) Cards were
designed for use in ISA slots, and the current Ultra T1(E1) cards are PCI. The newer PCI versions are available with either a single
T1(or E1) interface or with a dual T1(or E1) interfaces.
The ULTRA T1 (E1) features in-service monitoring of T1 (E1) circuit connections, including 64-Kbps channels within a T1 or E1.
It provides out-of-service troubleshooting such as bit-error-rate testing. Drop and Insert capabilities provide access to DS0s without
disrupting service.
The ULTRA T1 (E1) can be used for routine testing of errors, such as bit errors, frame errors, and bipolar violation; signals,
including received frequency, received signal level, and data bits; and timing including signal-loss seconds, test length etc. Alarm
monitoring and time-stamped logging provide windows into the network performance.
The ULTRA T1 (E1) emulates and decodes all 24 (32) channels simultaneously for Signalling Bits, Power Level, Frequency and
Multi-Frame Data. DTMF/MF generation and detection, signalling bit manipulation and recording provide complete signalling capabilities.
Graphical views simplify the understanding of PCM data. Time-domain is presented using an oscilloscope display, and frequency
domain using spectral displays.
Voice Frequency Access: Besides providing access to in-band PCM data, the ULTRA T1 (E1) provides VF interface for monitoring
and inserting audio with Drop and Insert. The unit also provides convenient handset interface for voice over the T1 or E1 line.
Remote testing and monitoring can be done by remoting the PC using familiar software.
Precision Delay Measurement under basic software measures the Round trip Delay of a system. Round trip delay measurement is done
by sending a BER pattern with the insertion of an errored bit and timing the reception of the errored bit. Measurement is precise and
accurate to the microsecond level. A delay up to 8 seconds can be measured. The internal delay of the card is subtracted from the round
trip delay.
New Generation High Density T1 and E1 Boards
The new generation T1 and E1 boards can process hundreds of channels or timeslots simultaneously on T1 and E1 lines. These
boards are smaller, more efficient, and significantly faster as compared to older PCI boards.
Comparison and advantages of the new generation High Density T1/E1 cards with the older Dual PCI T1/E1 cards are given in
the following table.
| Feature |
High Density Dual T1/E1 cards(New generation cards) |
Dual PCI T1/E1Cards (old cards) |
| Size (form factor) |
Smaller (more than two inches shorter)
Benefit: Fits inside smaller form factor PCs |
Larger |
| Speed |
Significantly Faster - uses 32 bit wide bus, and is built on Direct Memory Access (DMA) technology
Benefit: DMA technology prevents conflicts with existing devices |
Uses only 16-bit wide bus and uses older interrupt driven technology |
| PC CPU Utilization |
Very CPU efficient. Compatible with Hyperthreading and Dual Processor architectures
Benefit:The on-board processing and the DMA technology make this board very CPU efficient. This will allow the
user to put up to 12 boards per system supporting 24 independent T1/E1 ports |
CPU requirements impose a limit of 4 boards per system
Not compatible with Dual Processors or Hyperthreading |
| Highly improved on-board logic |
The new on-board chips are faster, and have larger memories. These chips can store the entire logic for supporting various
applications. Hence loading different logic to support different applications are no longer necessary
Benefit: Gives the user the ability to run special applications simultaneously and without "T1 E1 line interference"
associated with unloading and loading of multiple loads.Newer applications that exploit the above features are available
(as well as current applications are being enhanced), see below for more details |
Cannot run multiple applications that require separate loads simultaneously |
Detailed Description of Advantages
General Description
The new generation boards have item numbers HDT001 and HDE001 for "High Density Dual T1" and "High Density Dual E1".
These replace the older DPT001 and DPE001 boards. They can be distinguished from the DP-series boards by the letters "HD"
appearing on the card bracket immediately below the T1 or E1 designator (Earliest productions of this board were distinguished by
red "E1" or "T1" lettering.) The serial numbers follow the scheme below:
- HDT001s - 766xxx older DPT001s - 755xxx
- HDE001s - 866xxx older DPE001s - 855xxx
Smaller Size
GL's new "high density boards" are smaller, The new board's
dimensions are 4.2" x 7.1" vs. the older boards 4.2" x 9.2".
High Density and High Speed
The HD boards are significantly faster, and
significantly more efficient than the older boards. The new boards use DMA and a 32-bit wide bus; the older boards used an
interrupt driven scheme and a 16-bit bus; the older boards sometimes conflicted with interrupts shared by other devices.
CPU Usage
CPU utilization with the newer boards is negligible with increasing
boards in a system. With the older boards, there was a practical limit of 4 dual boards to a system - with limitations in overall
capability as well. One can easily put 12 new dual boards in one rack system running many applications on all 24 ports
simultaneously. For example, one can simulate echo on hundreds of timeslots by running simultaneously "delay/attenuate" on all
24 T1 ports on all timeslots.
Unlike older boards, HD Boards are compatible with dual processor motherboards and
software that simulates dual processors (i.e. hyperthreading).
Improved On-board Logic
- The newer boards use an upgraded FPGA to handle almost all specialized functions with a "single load" vs. multiple loads on
older cards. This permits special applications to be run simultaneously and without "T1 E1 line interference" associated with
unloading and loading of multiple loads. For example FDL applications can be run simultaneously with BERT or Error Insertion
applications.
- There are significant BERT enhancements incorporated into the FPGA hardware. These are sub-channel BERT, non-contiguous
timeslot BERT, user defined programmable patterns, independent transmit and receive BERT sections, and inverting patterns.
Bit error rate insertion has also been incorporated into the FPGA. User software to take advantage of these capabilities will
soon be developed. Xilinx loads "t1pass.bit" and "e1pass.bit" are modified to improve multichannel BERT performance.
- The FPGA will also handle "signaling bits", called CAS (Channel Associated Signaling). The older cards implemented this through
software. User software to take advantage of this capability will soon be developed.
- An application has been developed for the high density boards that make special use of the large FPGA on these boards.
This application simulates "single channel low echo path delays" and is a complement to the software version the
"delay/attenuate" software. While the older software implementation imposes an internal delay of 20ms, the newer hardware
implementation shortens the internal delay to as low as about 1 ms.
- Another special application that allows handling of "A-law all bits inverted" on T1 lines is included. In general any code
conversion such as inversion can be performed in the FPGA of the high density boards.
- Application FPGA registers are built into the application Xilinx (a control block for most operation conducted by the board)
and help in controlling various settings on the board that affect he logic operations applied to the T1/E1 stream. Applications
manipulate these registers when certain settings are applied by the user. End users are not expected to know the detail
specifications of these registers.This feature includes registers useful during remote debugging.
- Application Xilinx also includes XOR capability for voice band client.
Currently high density boards are only available in dual t1 or dual e1 port versions. Single port versions are not available.
Screenshots
(Note: these pages all take approximately 30 seconds to load when using a 28.8K modem)
With Basic Software:
With Optional Software:
Specifications
Physical Interface
| T1/E1 Signal |
RJ48c Connectors or Tx and Rx Bantam Jacks |
| Audio Signal |
Tx and Rx Mini Headphone Jacks (1/8 inch - diameter) or Bantam Jacks (600 ohms) |
| External Clock |
MCX or SMB Coaxial Jack |
| PC Interface |
ISA-AT-Style/PCI 2.1 Compliant for Cards
Parallel Port /PCMCIA Type II for Laptop Units. |
Environmental specifications
| Temperature |
Operating: 0 to 50° C
Storage: -50 to 70° C |
| Relative Humidity |
Operating: 10% to 90% (non-condensing)
Storage: 0% to 95% (non-condensing) |
| Altitude |
Operating: -100 to 12,000 ft.
Storage: -100 to 40,000 ft. |
T1/E1 Line Interface
| Line Code Format |
AMI or B8ZS(T1), HDB3(E1) |
| Framing Format |
D4, ESF, Unframed, CAS, CCS, CRC4 |
| Input Frequency |
1.544 Mbps (T1) or 2.048 Mbps (E1) |
| Input Impedance |
For Terminate and Monitor = 100 Ohms (T1), 120 Ohms (E1), For Bridge > 1000 Ohms |
| Input Level |
75 mV to 6V base to peak or -30 dBsx to -6 dBsx |
| Output Level |
3.0V ± 0.3 Base to Peak, Selectable 0-655 ft. Pulse Equalization Setting (T1 Short Haul)
or line build-outs for 0 dB to -22.5 dB (T1 Long Haul) |
| Receiver Interface |
Terminate, Monitor, and Bridge |
| Output Clock Source |
Recovered, Internal (+/- 1 ppm or 3 ppm), or External |
| Power |
T1
0.6 mAmp @ -5V min; 12.0 mAmp @ -5V max
0.76 mAmp @ +5V min; 13.5 mAmp @ +5V max
E1
0.6 mAmp @ -5V min; 12.0 mAmp @ -5V max
0.76 mAmp @ +5V min; 13.5 mAmp @ +5V max |
| Zero Suppression |
B7 Stuffing, Transparent, & B8ZS (T1) |
| Signaling |
Robbed-Bit or Clear Channel (Single and Dual PCI) |
| Alarm Detection and Generation |
T1
Yellow Alarm (B2 Suppressed-2nd MSB)
Yellow Alarm (S-Bit)
Yellow Alarm (00FF in FDL)
Blue Alarm (Framed or Unframed All Ones)
E1
Remote Alarm
Distant Multi frame Alarm
Signaling All Ones
Unframed All Ones |
Transmit
| T1/E1 Interface |
Hardware Compliant:
ANSI: T1.102, T1.403, T1.408
ITU: I.431, G.703, G.736, G.775, G.823
ETSI: ETS 300 166, ETS 300 233
AT&T 62411 |
PCM Channel Simulation Sources
| Synthesized Tone |
15 Hz to 3975 Hz selectable in 1 Hz steps, +3.0 dBm to -40.0 dBm in 0.1 steps selectable, Frequency Sweep |
| Dual Tone |
Single or any combination of tones |
| Supervision |
User defined states of A,B (C,D) bits |
| Signalling |
DTMF/MF Dialing Digits |
| File Playback |
User Created or Recorded file |
| Special Codes |
Milliwatt Codes, CSU Loop Up/Down Codes |
| Error Insertion |
Bipolar Violation, Blue Alarms, Yellow Alarms, Frame Error, CRC Errors, Bit Errors, Burst Frames, Fixed Error Rate,
Random Error Rate, Remote Alarm, Distant Multiframe Alarm |
PCM Channel Receiver
| Displays for All Channels |
Signalling Bits, Power Level, Frequency, Data |
| Graphical Displays |
Oscilloscope, Spectral, Spectrogram, Signal-to-Noise |
| Signalling |
DTMF/MF Dialed Digit Detection and Analysis |
| Recorder |
Record Full/Fractional T1/E1 Timeslots to Hard Disk File |
| Receiver Out-Of-Frame Criteria |
T1
2 of 4 Framing Bits
2 of 5 Framing Bits |
| Receiver Resync Options |
T1
10 Consecutive Ft or FPS bits
24 Consecutive Ft or FPS bits
Re sync Using only Ft or FPS bits
Re sync Using Both Ft and Fs or FPS and CRC |
| CAS Multi frame Sync Criteria |
E1
Fixed Re sync Criteria
Fixed and/or 0000XXXX in Two Consecutive Timeslot 16s
Frame Re sync Criteria
Fixed and/or Bit 2 in Timeslot 0 of Nonaligned Frames in Error on 3 Consecutive Occasions |
Facility Data Link
| T1 ESF Mode |
Transmit/ Receive Messages, Bit-Oriented Messages, and Files |
Drop and Insert
| Digital/Analog |
Any Contiguous set of digital Timeslots and/or Audio Input |
Pattern Generation
| BERT |
63(26-1), 511(29-1), 2047(211-1), 32767(215-1),
1048575(220-1), 8388607(223-1), QRSS, All Ones, All Zeros, 1:1, 1:7, 3-IN-24, User Defined 24- Bits,
Auto Logic & BPV error insertion from 10-2 - 10-9 for selectable 56/64 Kbps channels |
| International, National & Extra Bits |
User Defined (E1) |
Result Display and Logging
| BERT |
Bit Errors, Bit Error Rate, Error Seconds, Error Free Seconds, %EFS, Severely Error Seconds, %SES, Degraded
Minutes, %Dmin, Loss Pattern Sync Count, Loss of Sync Seconds, Available Seconds, %Available Seconds, Unavailable Seconds.
Bipolar Violations, BPV Rate, BPV Seconds, BPV Free Seconds, Frame Errors, FE Rate, FE Seconds, FE Free Seconds, with detailed
logging into disk file |
| Alarms |
Resync In Progress, Loss of Signal, Blue Alarm, Change Of Frame Alignment, Bipolar Violation, Frame Error,
Carrier Loss, Yellow Alarm, Out of Frame Events Counter, Errored Superframe Counter, Bipolar Violations Counter, Remote Alarm,
Distant Multiframe Alarm, Signalling All Ones, CAS Multiframe Error, CRC4 Error |
Audio Channel Access
| VF Input/Output Impedance |
600 Ohms |
| Audio Monitoring |
Built-in-Speaker or External Speaker Attachment |
| Volume Control |
User Specified Software Controller |
| Audio Insertion |
Selected DS0 replaced with inserted audio from VF Input or Handset with selected gain |
Propagation Delay
| Measurement |
Up to 2 Seconds |
Precision Delay
| Measurement |
Up to 8 Seconds |
Computer Requirement
| Pentium or better with 100M bytes of free space available on hard disk, Win 95/98/NT, 32M byte RAM, 1.44M(3.5 inch) drive,
AT-Style ISA expansion slots or PCI expansion slots. |
Physical Dimensions
| Dimensions |
7.0 L x 4.2 H (Single ISA and PCI card)
9.2 L x 4.2 H (Dual PCI card)
7.1 L x 4.2 H
(Dual HD card)
8.2 L x 5.8 H x 1.8 H (Laptop Analyzers) |
Specifications subject to change without notice.
Latest Software
FOR CURRENT USERS OF ULTRA T1/E1 CARDS:
Click here to acquire the latest software from the download page.
Application Notes
Buyer's Guide
Please Note: The XX in the Item No. refers to the hardware platform, listed at the bottom of the Buyer's Guide, which
the software will be running on. Therefore, XX can either be UT, UE, PCT, or PCE depending upon the hardware.
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![Main T1/E1 Application Screen](javascript:myOpen("images/main.gif")){kind=link}
![Ultra T1/E1 BERT Display](javascript:myOpen("images/lapber.gif")){kind=link}
![Ultra T1/E1 Precision Delay Measurement](javascript:myOpen("images/precisiondelay1.jpg")){kind=link}
![Ultra T1/E1 Transmit Tone](javascript:myOpen("images/txtone.gif")){kind=link}
![Ultra T1/E1 Transmit Multiframe](javascript:myOpen("images/txmulti.gif")){kind=link}
![Ultra T1/E1 Signalling Bits](javascript:myOpen("images/signal.gif")){kind=link}
![Ultra T1/E1 Tx/Rx Loop](javascript:myOpen("images/txrxloop.gif")){kind=link}
![Ultra T1/E1 Monitor Display](javascript:myOpen("images/lpmontr.gif")){kind=link}
![Ultra T1/E1 VF Drop & Insert](javascript:myOpen("images/vfdrop.gif")){kind=link}
![Ultra T1/E1 Power, Frequency Displays](javascript:myOpen("images/powrfreq.gif")){kind=link}
![Ultra T1/E1 Bytes Display](javascript:myOpen("images/bytes.gif")){kind=link}
![Ultra T1/E1 Time Slot Data Display](javascript:myOpen("images/timeslot.gif")){kind=link}
![Ultra T1/E1 Multiframe Data Display](javascript:myOpen("images/lpmltfrm.gif")){kind=link}
![Ultra T1/E1 Real Time Bit Map Display](javascript:myOpen("images/bitmap.gif")){kind=link}
![Ultra T1/E1 Time Slot Oscilloscope Display](javascript:myOpen("images/oscilloscope.gif")){kind=link}
![Ultra T1/E1 Time Slot Spectral Display](javascript:myOpen("images/spectral1.gif")){kind=link}
![Ultra T1/E1 Transmit Guassian Noise](javascript:myOpen("images/txguassnoise.gif")){kind=link}
![Ultra T1/E1 Error Insertion](javascript:myOpen("images/errins.gif")){kind=link}
![Ultra T1/E1 Real Time Multiframes](javascript:myOpen("images/realtimemulti.gif")){kind=link}
![Ultra T1/E1 Configuration](javascript:myOpen("images/t1config.gif")){kind=link}
![Ultra T1/E1 Record from Multiple Cards](javascript:myOpen("images/recfrommultiplecards.gif")){kind=link}
![View and Save Data](javascript:myOpen("images/fdlview.gif")){kind=link}
![Playback File](javascript:myOpen("images/fdltxhdlc.gif")){kind=link}
![FDL Decode and Analysis](javascript:myOpen("images/fdlanalysis.gif")){kind=link}
![Ultra T1/E1 Call Capture & Analysis Setup](javascript:myOpen("images/ccapture.gif")){kind=link}
![Ultra T1/E1 Signalling Bits Recording](javascript:myOpen("images/sgnlrcsm.gif")){kind=link}
![Ultra T1/E1 Measure Loop Delay/ERL](javascript:myOpen("images/delayerl.gif")){kind=link}
![Ultra T1/E1 Delay Attenuate Timeslots](javascript:myOpen("images/delayattenuate.gif")){kind=link}
