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OC-3 / STM-1 OC-12 / STM-4 Analyzer
for PoS Mode

Overview

PoS is a highly scalable layer 2 protocol that uses PPP encapsulation to carry IP packets directly in SONET/SDH networks. Currently it carries a majority of the Internet traffic because it can make efficient use of existing SONET infrastructure. PoS uses practically all optical interfaces, and is defined by the Internet Engineering Task Force (IETF) in the following RFC documents:

  • RFC 1661 The Point-to-Point Protocol (PPP)

  • RFC 1662 PPP in HDLC framing

  • RFC 2615 PPP over SONET / SDH

  • SONET is described in BellCore GR-253-core

  • SDH is described in ITU G.707

The format and steps below show how IP packets are mapped into SONET / SDH payloads:

  • Apply 20 bytes IP header for each IP packet

  • PPP packet headers and HDLC framing are applied to each IP Datagram

  • Frame check sequences (FCS) and octet stuffing are appended to the IP Datagram

  • Idle flags are inserted in between frames (IP Packets)

  • Final scrambling of the IP Datagram and synchronous mapping by octet into the SONET/SDH frame

The above procedure is continued for remaining IP Datagrams that make up the IP packet.

PoS packet structure

GL's LightSpeed1000™ analyzer supports Packet over SONET / SDH (Pos) at OC-3/STM-1 and OC-12/STM-4 at full rates over dual interfaces. Access, capture, analysis, and emulation of PPP and HDLC, all carrying IP traffic in real-time makes this card useful to many applications including Routing, Deep Packet Inspection, and other Internet traffic applications. Multiple cards can be installed in a PC making it scalable to monitor or generate OC-3 or OC-12 traffic on multiple ports. Each port on a card can work independent of others, which extends analyzer's flexibility as test equipment.


Main Features

  • Supports signal rates of 155.52 Mbps for OC-3 and 622.08 Mbps for OC-12 interface.

  • Capture and analyze Point-to-Point Protocol (PPP) over SONET/SDH as per RFC 2615.

  • Wire speed cell generation and processing on single or multiple ports using internal logic.

  • Supports payload scrambling of polynomial 1+X^43.

  • Supports up to 16 128 bit hardware filters. All filters are protocol independent and provide a greater flexibility. Deep packet inspection becomes easier with support of filter offset feature.

  • SONET Statistics: Link State, Line Speed, Section LOS, Section LOF, Section BIP (B1), Line AIS, Line RDI, Line REI (FEBE), Line BIP (B2), Path AIS, Path RDI, Path REI (FEBE), Path BIP (B3).

  • Packet statistics: Tx/Rx Byte Count, Tx/Rx Packet Count, Rx FCS Error Count, Rx Abort Packet Count, Rx Minimum and Maximum Packet Length Violation Error Count.

  • IP Statistics: IP Packets Received, IP Checksum Errors, , UDP data over IP Layer frame count

  • Loopback options include: Software Rx-to-Tx memory loopback, line loopback, diagnostic loopback, and PL3 loopback options.

  • Bit Error Rate Test module supports generation and analysis of payloads at wire speed. Supports many PRBS patterns and user-defined patterns as payload. Report on error count, error rate, sync loss, SES, and others is provided.

  • Capture data to file on individual ports, limited only by hard disk size.

  • PPP protocol analysis supported on single or multiple ports

  • Memory based transmit/receive test with incremented sequence number based data for each packet.

Basic Applications

Alarms and Error Counters Monitoring

The alarm and error monitoring window is provided for each of the OC-3/OC-12 port displays the detail status of the communication with the other end. Hardware LEDs are provided on the card to read line alarms.

Monitored alarms and counters include

  • Line errors such as OOF, LOS, LOF, AIS, RDI, and APSBF

  • FCS, Rx / Tx Abort, and MIN / MAX Length

  • Line, Path, and Section error counts

PoS Alarms

Software Loopback (Rx-To-Tx Memory Loopback)

Software memory loopback is used for diagnostic purposes. It loops all the received packets / cells from the SONET to the transmitting ports. This module uses both ports on the selected board.

The features include

  • selection of source and destination ports to transmit and receive packets/cells,
  • selection of ports on different boards for Tx and Rx, where multiple boards are used in a single chassis,
  • display of Tx and Rx information
  • loop back the data either in the page mode, 4K bytes at a time, or in the packet mode, packet by packet

PoS Memory Loopback

PoS Port Configuration

PoS Port Configuration allows users to select FCS type, control FCS stripping on Rx and FCS appending on Tx.

Rx FCS Bit Count - the receive side will check for 32 bit, 16 bit, or no FCS value at the frame end.

Rx FCS Octets Present - allows the receiving side to strip the FCS octets from received PoS frames or to leave the FCS octets as received.

Tx Append FCS allows adding the FCS octets at the end of every frame while transmitting.

PoS Port Configuration


Optional Applications

Following are the other applications are supported in LightSpeed1000™ PoS analyzer. Note that these applications require additional licenses. Visit the links below to get more information


Buyer's Guide

Item No Item Description
LTS201 OC-3 / STM-1 PoS Monitor, BERT, Tx/Rx Test, RAW
LTS301 OC-12 / STM-4 PoS Monitor, BERT, Tx/Rx Test, RAW
LTS203 OC-3 / STM-1 PoS and RAW Record / Playback
LTS303 OC-12 / STM-4 PoS and RAW Record / Playback
LTS205 OC-3 / STM-1 PoS Protocol Analysis
LTS305 OC-12 / STM-4 PoS Protocol Analysis
  Other Related Software
LTS200 OC-3 / STM-1 ATM Monitor, BERT, Tx/Rx Test
LTS300 OC-12 / STM-4 ATM Monitor, BERT, Tx/Rx Test
LTS202 OC-3 / STM-1 ATM and RAW Record / Playback
LTS302 OC-12 / STM-4 ATM and RAW Record / Playback
LTS204 OC-3 / STM-1 ATM Protocol Analysis
LTS304 OC-12 / STM-4 ATM Protocol Analysis
LTS206 OC-3 / STM-1 UMTS Protocol Analysis
LTS306 OC-12 / STM-4 UMTS Protocol Analysis
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